1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a DRAM or PSRAM (pseudo static RAM), which has a refresh control function, a method for controlling such a semiconductor memory device and an electronic information apparatus including the same semiconductor memory device.
2. Description of the Related Art
Conventionally, a DRAM/PSRAM requires a refresh operation for holding data therein. In the DRAM/PSRAM, a prescribed period of time is set so as to perform the refresh operation while inhibiting a CPU (central processing unit) from accessing the DRAM/PSRAM during the prescribed period of time.
However, for a system which is required to have fast processing ability, it is a great waste of time to set such a time period so as to inhibit the CPU from accessing memory, such as DRAM or PSRAM. In order to avoid such a great waste of time, for example, a xe2x80x9cmemory control devicexe2x80x9d disclosed in Japanese Laid-Open Patent Publication No. 7-161184 has been suggested. A control method used in this memory control device is described with reference to FIG. 6.
FIG. 6 is a block diagram showing a primary structure of a conventional semiconductor memory device including a conventional memory control device as disclosed in Japanese Laid-Open Patent Publication No. 7-161184. In FIG. 6, a memory block is divided into a plurality of memory banks which are not accessed simultaneously. The conventional memory control device includes refresh timers each corresponding to a respective one of the plurality of memory banks. Each refresh timer measures a period of time elapsed since a corresponding memory bank was refreshed. The conventional memory control device also includes a timer comparison section for comparing respective values of the refresh timers so as to determine a memory bank, which has not been refreshed for the longest period of time, among all the memory banks.
When a read/write access operation is performed with respect to the memory bank due to an external control signal (not shown), a refresh operation is performed simultaneously with the read/write cycle on one of the memory banks other than the memory bank, which is targeted for the read/write access operation, corresponding to the refresh timer having a greatest value, i.e., the memory bank which has not been refreshed for the longest period of time among all the memory banks other than the target memory bank.
When only the same memory bank is continuously accessed so that the same memory bank cannot be refreshed during a period of time for data to be held by the same memory bank, the conventional memory control device outputs a timeout signal to the same memory bank so as to inhibit the same memory bank from being accessed and to refresh the same memory bank.
Therefore, a refresh operation can be concealed so as not to be apparent to any external device when continuous accesses are not performed with respect to the same memory bank.
However, since the DRAM/PSRAM are random access memories, only the same memory bank can be continuously accessed. As described above, in the structure of the conventional memory control device, when the same memory bank is continuously accessed, the conventional memory control device outputs a timeout signal so as to inhibit the same memory bank from being accessed, and therefore the refresh operation can be performed on the same memory bank. However, if the conventional memory control device frequently outputs the timeout signal (so as to perform the refresh operation), a period of time occurs for which the same memory bank is continuously inhibited from being accessed, and therefore there is no sense in employing the conventional control method as described above.
In order to reduce the frequency of outputting the timeout signal, a possibility that only the same memory bank is accessed must be decreased. One method applicable to this end is to subdivide the memory block so as to increase the division number of the memory block (i.e., the number of memory banks).
However, as described above, in the conventional control method used in conjunction with the xe2x80x9cmemory control devicexe2x80x9d disclosed in the Japanese Laid-Open Patent Publication No. 7-161184, the memory control device is required to include the refresh timers each corresponding to a respective one of the memory banks. Each refresh timer measures a critical amount of time for a memory cell to hold data. Although a size of each refresh timer is not considerably large, a size of a circuit, which includes a plurality of refresh timers according to the number of memory banks, becomes large. Further, since the timer comparison section is required to compare values of all the refresh timers, when the number of memory banks is increased, the timer comparison section becomes complex and large.
On the other hand, since the number of memory banks cannot be increased, a size of each memory bank is increased. That is, a region to be activated for each access is increased in the memory bank, thereby causing an increase in consumption current. Further, whenever a read/write access operation is performed with respect to the memory bank due to the external control signal, a refresh operation is performed on another memory bank. Accordingly, two memory banks are always activated simultaneously. Since these two memory banks are simultaneously activated, the refresh operation is concealed so as not to be apparent to any external device, i.e., the memory access and the refresh operation are simultaneously performed in parallel. However, when the memory bank is sequentially requested to be read/written every 100 nanoseconds, the refresh operation is also performed every 100 nanoseconds while it is enough to perform the refresh operation with a frequency between several microseconds and several tens of microseconds. As a result, consumption current is increased by the unnecessary refresh operations.
According to one aspect of the present invention, there is provided a semiconductor memory device which includes: a memory block including a plurality of memory cells each including a transistor and a capacitor and storing information based on the presence of charges in the capacitor, the charges in the capacitor being held by a refresh operation, the memory block being divided into a plurality of memory banks such that the number of the memory banks is greater than a usually-prescribed number and the plurality of memory banks are not simultaneously accessed, the plurality of memory banks individually receiving access and refresh operations with respect to the memory cells; a time measurement section for measuring a critical amount of time for the memory cells to hold data; a plurality of memory circuits each storing refresh information which indicates that a corresponding memory bank is refreshed; a refresh address designation section for designating a refresh address in the corresponding memory bank; and a refresh control section for controlling the refresh operation with respect to each of the memory banks according to the designated refresh address and determining an unrefreshed memory bank based on the refresh information so as to perform the refresh operation with respect to the determined unrefreshed memory bank.
In one embodiment of this invention, the semiconductor memory device further includes a plurality of adjustment sections provided so as to respectively correspond to the memory banks and select any one of the refresh address and a normal access address based on a control signal from the refresh control section.
In one embodiment of this invention, the refresh control section controls an operation of the semiconductor memory device so as to inhibit access to a normal access address and prioritize the refresh operation with respect to the memory bank which is not refreshed within the critical amount of time for the memory cells to hold data.
In one embodiment of this invention, when normal access is performed with respect to the memory bank at a normal access address, the refresh control section controls the operation of the semiconductor memory device so as to simultaneously perform the refresh operation at the refresh address with respect to the plurality of memory banks except for the memory bank normally accessed at the normal access address.
According to another aspect of the present invention, there is provided a method for controlling a semiconductor memory device which includes the steps of: when normal access for a read/write operation is performed with respect to a memory bank in the semiconductor memory device due to an external control signal, checking refresh information stored in all memory circuits corresponding to their respective memory banks other than the memory circuit corresponding to the accessed memory bank so as to determine whether or not there is any unrefreshed memory banks other than for the accessed memory bank; when an unrefreshed memory bank is determined to be present based on the refresh information, refreshing the unrefreshed memory bank simultaneously with the normal access for a read/write operation to the other memory bank and storing refresh information which indicates that the unrefreshed memory bank has been refreshed; when a time measurement section outputs a timeout signal which indicates that a critical amount of time for memory cells to hold data has elapsed, checking the refresh information stored in the memory circuits corresponding to all the memory banks so as to determine whether or not all the memory banks have been refreshed; when an unrefreshed memory bank is determined to be present, refreshing the unrefreshed memory bank and storing the refresh information which indicates that the unrefreshed memory bank has been refreshed in the memory circuit corresponding to the unrefreshed memory bank; checking the refresh information stored in the memory circuits corresponding to all the memory banks once again so as to determine whether or not there is any memory bank which is left unrefreshed; when an unrefreshed memory bank is determined to be present based on the refresh information, refreshing the unrefreshed memory bank; repeating the checking and refresh operations until all the memory banks are refreshed; and incrementing a refresh address designation section for designating a refresh address at the time of performing the refresh operation after all the memory banks have been refreshed, wherein when all the memory banks have been refreshed before outputting the timeout signal, the refresh address designation section is incremented immediately after outputting the timeout signal.
In one embodiment of this invention, when normal access for a read/write operation is performed with respect to the memory bank in the semiconductor memory device due to the external control signal and/or when the timeout signal is output, the refresh operation is performed with respect to groups of the plurality of memory banks each group consisting of two or more memory banks.
In one embodiment of this invention, after the timeout signal is output, the refresh operation is performed with respect to an unrefreshed memory bank while inhibiting an access of the external control signal to the memory banks.
In one embodiment of this invention, in the memory bank targeted for normal access for a read/write operation due to the application of the external control signal, when a row address part obtained by decoding an address of a memory cell receiving the normal access is identical to a row address output by the refresh address designation section, the refresh information, which indicates that the memory bank targeted for the normal access has been refreshed, is stored in the memory circuit corresponding to the memory bank targeted for the normal access.
According to still another aspect of the present invention, there is provided an electronic information apparatus including the semiconductor memory device for processing information while performing memory and refresh operations.
Effects of the above-described structure will be described below. According to the present invention, the number of the plurality of memory banks is greater than the number of the memory banks used in the conventional control method, i.e., the number of the plurality of memory banks is greater than the number of the memory banks usually used, so as not to be simultaneously accessed. However, unlike the conventional control method, a plurality of refresh timers corresponding to the number of divided memory banks and the timer comparison section for comparing values of the refresh timers are not included in the semiconductor memory device of the present invention. Instead of including the plurality of refresh timers and the timer comparison section, the semiconductor memory device includes a single refresh timer and small-scale circuits, such as memory circuits each having a size of substantially one bit and storing information which indicates whether or not a corresponding memory bank is refreshed and adjustment circuits for refresh address and normal access (read/write operations due to an externally-input control signal). Therefore, even when the memory block is divided into a plurality of memory banks, there is no adverse effect as associated with the conventional control method, which includes a considerable increase in size of an internal circuit due to a plurality of refresh timers, and a considerable increase in size and complexity of the timer comparison section. Further, a size of the internal circuit of the semiconductor memory device is reduced as compared to the conventional memory control device, so that an entire size of the semiconductor memory device is not increased. Therefore, it is possible to easily divide the memory block into a number of memory banks, considerably reduce the frequency of outputting the timeout signal from the refresh timer to the refresh control circuit, and reduce consumption current required for the refresh operation without increasing an entire size of the semiconductor memory device.
Further, the semiconductor memory device according to the present invention includes the memory circuits corresponding to the respective memory banks which store historical information which indicates whether or not the corresponding memory banks have been refreshed. Therefore, even if the reading/writing access is frequently requested with respect to any one of the memory banks, the memory banks which have been already refreshed are not refreshed again as conventionally required, and therefore unnecessary refresh operations are avoided. This leads to further reduction in consumption current for the refresh operation.
Thus, the invention described herein makes possible the advantages of providing: (1) a semiconductor memory device which can reduce the frequency of outputting a timeout signal for inhibiting a memory access and performing a refresh operation and can reduce consumption current required for the refresh operation without increasing a size of an internal circuit; (2) a method for controlling such a semiconductor memory device; and (3) an electronic information apparatus including the same semiconductor memory device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.